LAUSR

Abstract In nMOS transistors the impact of positive bias temperature instability (PBTI) on the device performance is typically considered negligible and has thus been barely studied in the past. However, an accurate description of this phenomena requires and in depth understanding of the physical origin being responsible for the change of the device characteristics over time. For the assessment of PBTI in nanoscale SiON nMOS transistors we make use of the time-dependent defect spectroscopy (TDDS) and examine the device performance degradation at the single-defect level. Contrary to what is visible in large-area devices, our investigations clearly reveal that charge trapping at both electron and hole traps contributes to the overall drift of the threshold voltage in these devices. Furthermore we observe that hole traps account for around 20% of the total threshold voltage drift. To evaluate the impact of single-defects on the device performance we characterize the charge trapping kinetics of a number of defects, which can be explained by employing a two-state defect model. In our approach we observe charge trapping due to defect/channel interaction for electron traps and defect/gate interaction for hole traps. The extracted trap levels and trap depths clearly reveal that the electrically active electron traps reside closer to the SiON/Si interface while the hole traps are located closer to the poly-Si/SiON interface. Finally, the extracted trap parameters are fully consistent with defect candidates for electron and hole trapping from DFT calculations.