LAUSR

In this brief, a clock distribution scheme insensitive to supply voltage drift is proposed that minimizes variation of the clock propagation delay caused by the supply voltage change. While the overall clock distribution is composed of a current mode logic (CML) path and a CMOS path, most delay variations occur in the CMOS path. In the proposed scheme, delays in the CMOS path such as CML-to-CMOS converter (C2C) and inverters, are adjusted to compensate for the supply voltage drift. The bias generator provides self-generated bias voltages in response to the supply voltage drift for delay adjustment in the C2C and inverters. The proposed clock distribution path is fabricated in a 40 nm CMOS process with an active area of 0.004 mm2. Measured results show that the proposed scheme reduces the root-mean-square (RMS) jitter from 3.97 psRMS to 1.62 psRMS when the 1.1-V supply voltage is modulated by a sinusoidal wave of the 10-MHz, 100-mV peak-to-peak swing. Power consumption with differential 6-GHz clock is 11.02 mW over the clock path distance of 0.4 mm.